Low voltage power MOSFETs are often used in load switching applications. In load switching applications it is desirable to reduce the on-resistance (Rds) of the device. Specifically, the RdsA of the device needs to be minimized, where RdsA is the on-resistance of the device multiplied by the active area of the device. Additionally, low voltage power MOSFETs are commonly used in high frequency DC-DC applications. In these applications it is often desirable to maximize the device's switching speed. Three of the most important parameters for optimizing the switching speed are: 1) Rds×Qg; 2) Rds×QOSS; and 3) the ratio of Qgd/Qgs. First, the product of the Rds and the gate charge (Qg) is a measure of the device conduction and switching losses together. Qg is the sum of the gate to drain charge (Qgd) and the gate to source charge (Qgs). In the second parameter, QOSS is a measure of the capacitances that need to be charged and discharged whenever the device is switched on or off. Finally, minimizing the ratio of Qgd/Qgs reduces the possibility of the device turning on due to a large dV/dt when the device is being switched off.
Trench based MOSFETs, as shown in FIG. 1A, were designed in part in order to reduce RdsA of the device. The design of trench based MOSFETs allowed for the removal of the JFET structure that was present in planar MOSFETs. By eliminating the JFET, the cell pitch could be reduced. However, the basic trench based MOSFET does not have any charge balancing in the drift regions, and therefore causes an increase in the RdsA. Also, the relatively thin gate oxide generates a high electric field under the trench, which leads to a lower breakdown voltage. Low doping concentrations are needed in the drift region in order to support the voltage, and this increases the RdsA for structures with thinner gate oxides. Further, as cell pitch continues to decrease, the trench based MOSFET may become a less desirable choice because of the difficulty in reducing the thickness of the gate oxide further.
Previous attempts have been made to solve these problems through various designs. A first example is a shielded gate MOSFET as shown in FIG. 1B and described in U.S. Pat. No. 5,998,833 to Baliga. The use of a trench-based shield electrode connected to source potential instead of a larger gate electrode reduces the gate-to-drain capacitance (Co) of the MOSFET and improves switching speed by reducing the amount of gate charging and discharging needed during high frequency operation. However, the MOSFET device described by Baliga exhibits a high output capacitance because the source potential is capacitively coupled to the drain via the shield electrode. Also, in order to sustain the blocking voltage a thick oxide is required. Finally, complex processing is required in order to produce two electrically separated polysilicon electrodes within the same trench. The complexity of the fabrication is further accentuated when the pitch of the device is scaled downwards to the deep sub-micron level.
Finally, the MOSFET design shown in FIG. 1C and described in U.S. Pat. No. 4,941,026 to Temple, has certain characteristics that may be utilized to optimize the switching characteristics of a device. The device in Temple utilizes a two-step gate oxide with a thin layer of oxide near the top of the gate and a thicker layer of oxide in the bottom portion of the gate in order to create a device that has a low channel resistance and a low drift resistance. The thin upper portion of the gate oxide provides good coupling between the gate and body region which generates a strong inversion and low on-resistance in a channel next to the thin upper portion. The thicker gate oxide on the bottom creates a charge balancing effect and allows for the drift region to have an increased doping concentration. A higher doping concentration in the drift region decreases its resistance.
However, the device shown in FIG. 1C is not easily downwards scalable because it is highly susceptible to body contact misalignment errors. For example, if the pitch of the devices was scaled to the deep sub-micron level e.g., 0.5-0.6 μm, then the contact mask misalignment, relative to the gate, may greatly alter the characteristics of the device. In order to provide a good ohmic contact to the body region, an ohmic contact that is highly doped with dopants of the same conductivity type as the body region may be implanted after the contact mask has been used. If the contact mask is aligned too close to the gate, namely not landing exactly at the center of the silicon mesa, then highly doped implants used to generate the ohmic contact with the body may end up in the channel. If the highly doped ohmic region is in the channel, then the threshold voltage and the on-resistance of the device will be impacted. Also, if the contact mask is aligned too far away from the gate, then the turn on of the bipolar junction transistor (BJT) becomes an issue. Since the contact is further from the trench, the length of the body region is increased and therefore so is its resistance. As the resistance of the body region increases, it increases the voltage drop across the body region. The larger voltage drop across the body region will make it easier for the parasitic BJT to turn on and ruin the device.
Therefore, in order to fabricate deep sub-micron devices that are optimized for use as load switches and high frequency DC-DC applications there is a need for a device and method capable of self-aligning the contacts to the gate in order to prevent the aforementioned side effects.
It is within this context that embodiments of the present invention arise.